With global market of over $35 B, DRAM (dynamic random access memory) is the primary memory technology being used to implement main memory in virtually all computing systems, from embedded and mobile devices to desktops and servers. Current DRAM chips can ensure error-free data storage (except for radiation-induced soft errors), which largely simplifies the overall computing system design. Each DRAM cell contains one transistor and one capacitor, and the memory cell capacitor must have sufficiently large capacitance in order to ensure error-free data storage. Unfortunately, it becomes increasingly challenging to maintain the sufficiently large capacitance (hence error-free data storage) as the industry strives to sustain the 30-year DRAM bit cost reduction by scaling down the DRAM technology into the sub-25 nm regime.
This challenge has led to a tremendous amount of research efforts over the past decade on developing new memory technologies, e.g., STT-RAM (spin-transfer torque RAM), PCRAM (phase-change RAM), and ReRAM (resistive RAM). It has become clear that STT-RAM has the true potential to complement or even replace DRAM as the main memory in computing systems.
Nevertheless, STT-RAM cannot achieve comparable bit cost as DRAM, at least in the foreseeable future, and the scalability of STT-RAM technology faces similar data storage reliability challenges as well. In summary, technology scaling of DRAM and its potential competitor STT-RAM face formidable challenges, which are seriously threatening the future growth of the entire semiconductor and computing industry. Accordingly, a need exists that will allow for continued technology scaling, and hence memory bit cost reduction, using available technology.